Fully compatible with 2711 substitutes, compatible with sn8p2711 single chip microcomputer primary agent
Fully compatible with 2711 substitutes, compatible with sn8p2711 single chip microcomputer primary agent
Memory configuration ♦ 5 + 1 channel 12 bit ADC
OTP ROM: 1K * 16 bits. 5 external ADC inputs
Ram: 64 * 8 bits. 1 internal voltage measurement
Internal AD reference voltage (VDD, 4V, 3V, 2V)
♦ 4-layer stack buffer
♦ 2 8-bit timing / counters
♦ I / O pin configuration tc0: automatic loading timing / counter / pwm0 / buzzer output.
Bidirectional input and output: P0, P4, P5. Tc1: automatic loading timing / counter / pwm1 / buzzer output.
Unidirectional input: P0.4 is shared with the reset pin.
Pin with wake-up function: level conversion of P0. ♦ Built in watchdog timer and internal low-speed RC clock source
Pull up resistance: P0, P4, P5. （16KHz @3V，32KHz @5V）
External interrupt trigger edge:
P0.0 is controlled by pedge register. ♦ Dual system clock
P0.1 is triggered only by the falling edge. External high-speed clock: RC, maximum 10MHz.
External high-speed clock: crystal oscillator, maximum 16mhz.
♦ Layer 3 LVD internal high-speed clock: RC, maximum 16mhz.
Reset the internal low-speed clock of the system and power monitor: RC 16KHz (3V), 32kHz (5V)
♦ 5 interrupt sources ♦ Operation mode
Three internal interrupt sources: tc0, Tc1 and ADC. Normal mode: high and low speed clocks run at the same time.
2 external interrupt sources: INT0, INT1. Low speed mode: only the low speed clock operates.
Sleep mode: high and low speed clocks stop running.
♦ Powerful instruction set green mode: wake up periodically by tc0 timer.
One clock cycle per instruction cycle (1t)
The execution time of most instructions is one instruction cycle. ♦ Package (supported chip format)
The JMP instruction can directly address the entire ROM area. P-DIP 14 pins
The call instruction can directly address the entire ROM area. SOP 14 pins
The table lookup function (MOVC) can directly address the entire ROM area. SSOP 16 pins